ISA System Architecture, Third Edition
Part 1: The System Kernel
This section provides a detailed tutorial on how Intel X86 microprocessors communicate with memory and I/O devices. Included is the support logic which allows the microprocessor to communicate with 8- and 16-bit devices and detailed descriptions of the signals and timing involved in all Bus Cycle types.
Part 2: Memory Subsystems
The memory section provides a detailed theory of operation of RAM and ROM devices, along with implementations commonly used in ISA systems. The section also covers the concepts and terminology related to cache memory designs.
Part 3: The Industry Standard Architecture
This section provides a detailed discussion of the ISA Bus Architecture including ISA bus cycles and timing, along with ISA implementations of Interrupts, DMA, Real-Time Clock and Configuration RAM, Numeric Coprocessors, Keyboard/Mouse Interface, and Timers.
544 pages; ISBN 9780201409963
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Title: ISA System Architecture, Third Edition
Author: Tom Shanley; Don Anderson
Java For Everyone 2012 US$ 52.00 831 pages
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