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- Artech House 2007; US$ 105.00
Thanks to increasing power consumption and component density, localized hot spots are becoming a serious challenge in IC (integrated circuit) chip design so serious, in fact, that Intel recently had to yank a circuit because it was literally burning. For IC engineers grappling with high power dissipation and thermal issues, new droplet-based... more...
- CRC Press 2006; US$ 194.95
PART I SYNTHESIS TECHNIQUES Introduction Technology Issues Digital Microfluidic Biochips Microfluidic Biochip Design Challenges Book Outline Architectural-Level Synthesis Background High-Level Synthesis Methodology Simulation Experiments Module Placement Background Module Placement Problem Fault Tolerance... more...
- CRC Press 2011; US$ 167.95
Introduction Digital Microfluidic Technology Synthesis, Testing, and Pin-Constrained Design Techniques Protein Crystallization Book Outline Defect-Tolerant and Routing-Aware Synthesis Background Routing-Aware Synthesis Defect-Tolerant Synthesis Simulations Results ... more...
- Artech House 2010; US$ 109.00
Wafer-level testing refers to a critical process of subjecting integrated circuits and semiconductor devices to electrical testing while they are still in wafer form. Burn-in is a temperature/bias reliability stress test used in detecting and screening out potential early life device failures. This hands-on resource provides a comprehensive analysis... more...
- Springer New York 2012; US$ 129.00
This book provides a thorough methodology for automated design, test and diagnosis, and use of robust, low-cost, and manufacturable digital microfluidic systems. It focuses on the development of a CAD optimization framework for digital microfluidic biochips. more...
- CRC Press 2013; US$ 157.95
Fundamentals of Small-Delay Defect Testing Sudhakar M. Reddy and Peter Maxwell Timing-Aware ATPG K Longest Paths Duncan M. (Hank) Walker Timing-Aware ATPG Mark Kassab, Benoit Nadeau-Dostie, and Xijiang Lin Faster-than At-Speed Faster-than-at-Speed Test for Screening Small-Delay Defects Nisar Ahmed and Mohammad Tehranipoor Circuit Path... more...
- Springer International Publishing 2013; US$ 119.00
This volume encompasses the latest, innovative methods of testing three-dimensional integrated circuits, incorporating pre-bond and post-bond tests as well as the test optimization and scheduling necessary to ensure that 3D testing remains cost-effective. more...
- CRC Press 2002; US$ 209.95
INTRODUCTION Modeling and Simulation Issues Modeling and Simulation Needs Overview HIERARCHICAL MODELING MEFS Dynamic Modeling and Simulation at Circuit Level MEFS System-Level Modeling and Simulation Conclusion SYSTEMC-BASED HIERARCHICAL DESIGN ENVIRONMENT Suitability of Modeling Languages for Hierarchical Design Building Design Environment with... more...
- Springer New York 2011; US$ 129.00
This book introduces new techniques for detecting and diagnosing small-delay defects in integrated circuits. It details effective and scalable methodologies for screening and diagnosing small-delay defects. more...
- Springer New York 2013; US$ 129.00
This book details design technologies for green and sustainable computing. It examines the challenges of power efficiency and sustainability in various contexts, including system design, computer architecture, programming languages, compilers and networking. more...