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Most popular at the top
- Artech House 2007; US$ 105.00
Thanks to increasing power consumption and component density, localized hot spots are becoming a serious challenge in IC (integrated circuit) chip design so serious, in fact, that Intel recently had to yank a circuit because it was literally burning. For IC engineers grappling with high power dissipation and thermal issues, new droplet-based... more...
- CRC Press 2006; US$ 194.95
PART I SYNTHESIS TECHNIQUES Introduction Technology Issues Digital Microfluidic Biochips Microfluidic Biochip Design Challenges Book Outline Architectural-Level Synthesis Background High-Level Synthesis Methodology Simulation Experiments Module Placement Background Module Placement Problem Fault Tolerance... more...
- CRC Press 2011; US$ 167.95
Introduction Digital Microfluidic Technology Synthesis, Testing, and Pin-Constrained Design Techniques Protein Crystallization Book Outline Defect-Tolerant and Routing-Aware Synthesis Background Routing-Aware Synthesis Defect-Tolerant Synthesis Simulations Results ... more...
- Artech House 2010; US$ 109.00
Wafer-level testing refers to a critical process of subjecting integrated circuits and semiconductor devices to electrical testing while they are still in wafer form. Burn-in is a temperature/bias reliability stress test used in detecting and screening out potential early life device failures. This hands-on resource provides a comprehensive analysis... more...
- Springer New York 2012; US$ 129.00
Describes practical design automation tools that address different design problems (e.g., synthesis, droplet routing, control-pin mapping, testing and diagnosis, and error recovery) in a unified manner Applies test pattern generation and error-recovery techniques for digital microfluidics-based biochips Uses real bioassays as evaluation examples,... more...
- CRC Press 2013; US$ 157.95
Fundamentals of Small-Delay Defect Testing Sudhakar M. Reddy and Peter Maxwell Timing-Aware ATPG K Longest Paths Duncan M. (Hank) Walker Timing-Aware ATPG Mark Kassab, Benoit Nadeau-Dostie, and Xijiang Lin Faster-than At-Speed Faster-than-at-Speed Test for Screening Small-Delay Defects Nisar Ahmed and Mohammad Tehranipoor Circuit Path... more...
- Springer International Publishing 2013; US$ 119.00
Provides a comprehensive guide to the challenges and solutions for the testing of TSV-based 3D stacked ICs Includes in-depth explanation of key test and design-for-test technologies, emerging standards, and test- architecture and test-schedule optimizations Encompasses all aspects of test as related to 3D ICs, including pre-bond and post-bond test... more...
- CRC Press 2002; US$ 209.95
INTRODUCTION Modeling and Simulation Issues Modeling and Simulation Needs Overview HIERARCHICAL MODELING MEFS Dynamic Modeling and Simulation at Circuit Level MEFS System-Level Modeling and Simulation Conclusion SYSTEMC-BASED HIERARCHICAL DESIGN ENVIRONMENT Suitability of Modeling Languages for Hierarchical Design Building Design Environment with... more...
- Springer New York 2011; US$ 129.00
Provides an introduction to VLSI testing and diagnosis, with a focus on delay testing and small-delay defects Presents the most effective techniques for screening small-delay defects, such as long path-based, slack-based, critical fault-based, and noise-aware methodologies Shows readers to use timing information for small-delay defect diagnosis,... more...
Hardware/Software Co-Design and Optimization for Cyberphysical Integration in Digital Microfluidic BiochipsSpringer International Publishing 2014; US$ 119.00
Takes a transformative, "cyber physical" approach towards achieving closed-loop and sensor feedback-driven biochip operation under program control Presents a "physically-aware" system reconfiguration technique that uses sensor data at intermediate checkpoints to dynamically reconfigure biochips Enables readers to simplify the structure of biochips,... more...