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Robustness and Usability in Modern Design Flows
Springer 2008; US$ 109.99The size of technically producible integrated circuits increases continuously. But the ability to design and verify these circuits does not keep up with this development. Therefore today??'s design flow has to be improved to achieve a higher productivity. In Robustness and Usability in Modern Design Flows the current design methodology and verification... more...
Quality-Driven SystemC Design
Springer 2009; US$ 99.99Faced with the steadily increasing complexity and rapidly shortening time-to-market requirements designing electronic systems is a very challenging task. To manage this situation effectively the level of abstraction in modeling has been raised during the past years in the computer aided design community. Meanwhile, for the so-called system-level design... more...
Debugging at the Electronic System Level
Springer 2010; US$ 99.99Debugging becomes more and more the bottleneck to chip design productivity, especially while developing modern complex integrated circuits and systems at the Electronic System Level (ESL). Today, debugging is still an unsystematic and lengthy process. Here, a simple reporting of a failure is not enough, anymore. Rather, it becomes more and more important... more...
Towards a Design Flow for Reversible Logic
Springer 2010; US$ 99.99The development of computing machines found great success in the last decades. But the ongoing miniaturization of integrated circuits will reach its limits in the near future. Shrinking transistor sizes and power dissipation are the major barriers in the development of smaller and more powerful circuits. Reversible logic provides an alternative that... more...
High Quality Test Pattern Generation and Boolean Satisfiability
Springer 2012; US$ 99.99This book provides an overview of automatic test pattern generation (ATPG) and introduces novel techniques to complement classical ATPG, based on Boolean Satisfiability (SAT). A fast and highly fault efficient SAT-based ATPG framework is presented which is also able to generate high-quality delay tests such as robust path delay tests, as well as tests... more...
Advanced BDD Optimization
Springer 2005; US$ 149.99VLSI CAD has greatly benefited from the use of reduced ordered Binary Decision Diagrams (BDDs) and the clausal representation as a problem of "Boolean Satisfiability" (SAT), e.g. in logic synthesis, verification or design-for-testability. In recent practical applications, BDDs are optimized with respect to new objective functions for design space exploration. more...
Test Pattern Generation using Boolean Proof Engines
Springer 2009; US$ 109.99Gives an introduction to ATPG. This work reviews the basic concept and classical ATPG algorithms. It also considers the formulation as a SAT problem. It covers efficient instance generation, encoding of multiple-valued logic, usage of various fault models, and detailed experiments on multi-million gate designs. more...
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