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The Verilog® Hardware Description Language

The Verilog® Hardware Description Language by Donald E. Thomas
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xv From the Old to the New xvii Acknowledgments xxi 1 Verilog – A Tutorial Introduction 1 Getting Started 2 A Structural Description 2 Simulating the binaryToESeg Driver 4 Creating Ports For the Module 7 Creating a Testbench For a Module 8 11 Behavioral Modeling of Combinational Circuits Procedural Models 12 Rules for Synthesizing Combinational Circuits 13 14 Procedural Modeling of Clocked Sequential Circuits Modeling Finite State Machines 15 Rules for Synthesizing Sequential Systems 18 Non-Blocking Assignment ("
Springer US; May 2007
404 pages; ISBN 9780306476662
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Title: The Verilog® Hardware Description Language
Author: Donald E. Thomas; Philip R. Moorby
 
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